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7
VLIW Microprocessor Hardware Design

VLIW Microprocessor Hardware Design

Lee Weng Fook
اللغة:
english
ملف:
PDF, 3.08 MB
0 / 0
english
20
Processor Design System On Chip Computing for ASICs and FPGAs J Nurmi Springer 2007

Processor Design System On Chip Computing for ASICs and FPGAs J Nurmi Springer 2007

Unknown
عام:
2007
اللغة:
english
ملف:
LIT , 13.71 MB
0 / 0
english, 2007
21
Processor Design: System-On-Chip Computing for ASICs and FPGAs

Processor Design: System-On-Chip Computing for ASICs and FPGAs

Jari Nurmi (Editor)
عام:
2007
اللغة:
english
ملف:
PDF, 8.50 MB
0 / 5.0
english, 2007
24
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems

Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems

Vittorio Zaccaria, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano (auth.)
عام:
2004
اللغة:
english
ملف:
PDF, 8.97 MB
0 / 0
english, 2004
25
Instruction-Level Parallelism: A Special Issue of The Journal of Supercomputing

Instruction-Level Parallelism: A Special Issue of The Journal of Supercomputing

Richard Draper, John Riganati (auth.), B. R. Rau, J. A. Fisher (eds.)
عام:
1993
اللغة:
english
ملف:
PDF, 5.94 MB
0 / 0
english, 1993
28
Fine- and Coarse-Grain Reconfigurable Computing

Fine- and Coarse-Grain Reconfigurable Computing

K. Tatas, K. Siozios, D. Soudris (auth.), Stamatis Vassiliadis, Dimitrios Soudris (eds.)
عام:
2008
اللغة:
english
ملف:
PDF, 7.26 MB
0 / 0
english, 2008
34
Computer Systems: Architectures, Modeling, and Simulation: Third and Fourth International Workshops, SAMOS 2004, Samos, Greece, July 21-23, 2004 and July 19-21, 2004. Proceedings

Computer Systems: Architectures, Modeling, and Simulation: Third and Fourth International Workshops, SAMOS 2004, Samos, Greece, July 21-23, 2004 and July 19-21, 2004. Proceedings

Stamatis Vassiliadis, Georgi Gaydadjiev, Koen Bertels, Elena Moscu Panainte (auth.), Andy D. Pimentel, Stamatis Vassiliadis (eds.)
architecture
memory
processor
instruction
implementation
reconfigurable
processing
network
systems
architectures
simulation
figure
operations
execution
exploration
chip
processors
signal
configuration
compiler
parallel
units
approach
graph
fpga
synthesis
models
dataflow
modeling
embedded
dsp
algorithm
tools
operation
vector
mapping
shown
cache
cycle
platform
implemented
input
proc
specific
constraints
required
consumption
computation
array
components
عام:
2004
اللغة:
english
ملف:
PDF, 11.62 MB
0 / 0
english, 2004
40
VLSI-SoC: At the Crossroads of Emerging Trends: 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6–9, 2013, Revised and Extended Selected Papers

VLSI-SoC: At the Crossroads of Emerging Trends: 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6–9, 2013, Revised and Extended Selected Papers

Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis (eds.)
input
circuit
output
gate
scan
circuits
shown
different
memory
faults
algorithm
optimization
variables
architecture
method
modulator
passive
approach
noise
implementation
sizing
matching
clutr
delay
proposed
presented
estimation
inputs
step
matrix
gates
values
frequency
first
row
bits
fault
pixels
pixel
vliw
processing
signal
column
decoder
stereo
fpga
coordinates
filter
systems
processor
عام:
2015
اللغة:
english
ملف:
PDF, 21.65 MB
0 / 0
english, 2015
42
Mikrocontroller und Mikroprozessoren

Mikrocontroller und Mikroprozessoren

Uwe Brinkschulte, Theo Ungerer
عام:
2010
اللغة:
german
ملف:
PDF, 3.40 MB
0 / 5.0
german, 2010
43
Mikrocontroller und Mikroprozessoren

Mikrocontroller und Mikroprozessoren

Prof. Dr. Uwe Brinkschulte, Prof. Dr. Theo Ungerer (auth.)
عام:
2002
اللغة:
german
ملف:
PDF, 11.98 MB
0 / 0
german, 2002
48
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design: 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design: 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers

Michael Muehlberghuber, Christoph Keller (auth.), Andreas Burg, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis (eds.)
memory
processor
architecture
output
network
gate
fault
voltage
operation
shown
core
chip
pixel
gates
implementation
layer
parallel
clock
device
pixels
faults
proposed
faulty
input
dynamic
memories
processors
mapping
static
array
shows
vdd
processing
projection
neighbor
approach
vliw
vlsi
θi
figure
required
wires
instruction
router
compared
algorithm
different
circuits
layers
interpolation
عام:
2013
اللغة:
english
ملف:
PDF, 15.33 MB
0 / 0
english, 2013